1. Field of the Invention
The present invention relates to a semiconductor device and a carrier thereof, and more particularly to a chip package and a coreless package substrate thereof.
2. Description of Related Art
In the semiconductor industry, an integrated circuit (IC) is fabricated through three phases including an IC design, an IC process and an IC packaging. In the IC process, a chip is fabricated by forming ICs on the wafer and then dicing the wafer. A wafer has an active surface, which generally refers to a surface having active devices thereon. After forming the ICs on the wafer, a plurality of bonding pads are disposed on the active surface of the chip and the chip finally made by dicing the wafer can be electrically connected to an external carrier via the bonding pads. While the chip is connected to a carrier by using wire bonding or flip chip bonding, the bonding pads of the chip can be electrically connected to the contacts of the carrier to form a chip package. The carrier can be, for example, a leadframe or a package substrate.
In a flip chip bonding technology, prior to dicing the wafer a plurality of bumps are usually formed on the bonding pads on the wafer active surface such that the chip can be electrically connected to an external substrate. The bumps are usually arranged in an area array on the chip active surface so that a chip package with high contact count and high contact density can be obtained, such as the flip chip/ball grid array package broadly used in the semiconductor packaging field. Unlike the wire bonding, the bumps in a flip chip bonding provide shorter transmission paths between the chip and the carrier to effectively promote the electrical performance of a chip package.
FIG. 1 is a schematic cross-sectional view of a conventional flip chip package. Referring to FIG. 1, a conventional flip chip package 100 includes a substrate 110, a chip 120, a plurality of solder bumps 130, an underfill 140 and a plurality of solder balls 150. The substrate 110 includes an interconnection structure 112, which has an inner circuit 112a, a carrying surface 112b and a contact surface 112c, wherein the inner circuit 112a has a plurality of contact pads 112d disposed on the contact surface 112c. In addition, the chip 120 is disposed on the carrying surface 112b and electrically connected to the contact pads 112d through the solder bumps 130 and the inner circuit 112a. The underfill 140 is disposed between the chip 120 and the substrate 110 and encapsulates the solder bumps 130. The underfill 140 is used for protecting the solder bumps 130 and playing a buffering role to reduce a thermal strain mismatch in manufacturing processes. The solder balls 150 are disposed on the contact pads 112d respectively for being electrically connected to the next level electronic devices, such as a printed circuit board (PCB) (not shown in FIG. 1).
The interconnection structure 112 includes a dielectric core layer 112e, a plurality of plating through holes (PTHs) 112f, a plurality of organic dielectric layers 112g, a plurality of conductive vias 112h and a plurality of wiring layers 112i. The plating through holes (PTHs) 12f pass through the dielectric core layer 112e and each conductive via 112h passes through one of the organic dielectric layers 112g. Besides, two wiring layers 112i are electrically connected to each other through at least one plating through hole (PTH) 112f or through at least one conductive via 112h. Thus, the plating through holes (PTHs) 112f, the conductive vias 112h and the wiring layers 112i form the above-described inner circuit 112a. In the conventional flip chip package however, the pitch of the plating through holes (PTHs) 112f is hard to be reduced, which becomes a major bottleneck while the layout density of the substrate 110 is increased.